library IEEE;
use ieee.std_logic_1164.all;
use work.package_alu.all;


entity alu is
	port(a,b: in	std_logic_vector (7 downto 0);
		 sel : in	std_logic_vector (3 downto 0);
 		 cin : in   std_logic;
		 y	 : out	std_logic_vector (7 downto 0)
		 );
end alu;

architecture arch_alu of alu is
	signal logic : std_logic_vector(7 downto 0);
	signal arit : std_logic_vector(7 downto 0);
begin
	u1:arit_unit port map (a, b, sel(2 downto 0), cin, arit);
	u2:logic_unit port map (a, b, sel(2 downto 0), logic);
	u3:mux port map (arit, logic, sel(3), y);
end arch_alu;